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1 features ? 3.0v to 3.6v read/write burst read performance ?< 100 mhz (ras latency = 2, cas latency = 6), 10 ns cycle time t sac = 7 ns ?< 75 mhz (ras latency = 2, cas latency = 5), 13 ns cycle time t sac = 8 ns ?< 50 mhz (ras latency = 1, cas latency = 4), 20 ns cycle time t sac = 9 ns mrs cycle with address key programs ? ras latency (1 and 2) ? cas latency (2 ~ 8) ? burst length: 4, 8 ? burst type: sequential and interleaved word selectable organization ? 16 (word mode)/x 32 (double word mode) sector erase architecture ? eight 256k word or 128k double word (4-mbit) sectors independent asynchronous boot block ? 8k x 16 bits with hardware lockout fast program time ? 3-volt, 100 s per word/double word typical ? 12-volt, 30 s per word/double word typical fast sector erase time ? 2.5 seconds at 3 volts ? 1.6 seconds at 12 volts low-power operation ?i cc read = 75 ma typical input and output pin continuity test mode optimizes off-board programming package: ? 86-pin tsop type ii with off-center parting line (ocpl) for improved reliability lvttl-compatible inputs and outputs description the at49ld3200 or at49ld3200b sflash ? is a synchronous, high-bandwidth flash memory fabricated with atmel?s high-performance cmos process technology and is organized either as 2,097,152 x 16 bits (word mode) or as 1,048,576 x 32 bits (double word mode), depending on the polarity of the word pin (see pin function descrip- tion table). synchronous design allows precise cycle control. i/o transactions are possible on every clock cycle. all operations are synchronized to the rising edge of the system clock. the range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high-band- width, high-performance memory system applications. the at49ld3200b will automatically activate the asynchronous boot block after power-up, whereas with the at49ld3200, the asynchronous boot block can be acti- vated through mode register set. the synchronous dram interface allows designers to maximize system performance while eliminating the need to shadow slow asynchronous flash memory into high- speed ram. the 32-megabit sflash device is designed to sit on the synchronous memory bus and operate alongside sdram. 32-megabit (1m x 32 or 2m x 16) high-speed synchronous flash memory at49ld3200 at49ld3200b sflash ? rev. 1940b?11/01
2 at49ld3200(b) 1940b?11/01 to maximize system manufacturing throughput the at49ld3200(b) features high- speed 12-volt program and erase options. additionally, stand-alone programming cycle time of individual devices or modules is optimized with atmel?s unique input and output pin continuity test mode. pin configuration tsop (type ii) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 vcc dq0 vccq dq16 dq1 vssq dq17 dq2 vccq dq18 dq3 vssq dq19 mr vcc dqm nc cas ras cs word a12 a11 a10 a0 a1 a2 nc vcc nc dq4 vssq dq20 dq5 vccq dq21 dq6 vssq dq22 dq7 vccq dq23 vcc vss dq31 vssq dq15 dq30 vccq dq14 dq29 vssq dq13 dq28 vccq dq12 nc vss nc vpp we clk cke a9 a8 a7 a6 a5 a4 a3 nc vss nc dq27 vccq dq11 dq26 vssq dq10 dq25 vccq dq9 dq24 vssq dq8 vss
3 at49ld3200(b) 1940b ? 11/01 pin function description pin name input function clk system clock active on the rising edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk and cke. cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disables input buffers for power- down in standby mode. a0 - a12 address row/column addresses are multiplexed on the same pins. row address: ra 0 ~ ra 12 , column address: ca 0 ~ ca 6 (x32), ca 0 ~ ca 7 (x16) ras row address strobe latches row addresses on the rising edge of the clk with ras low. enables row access. cas column address strobe latches column addresses on the rising edge of the clk with cas low. enables column access. mr mode register set enables mode register set with mr low. (simultaneously cs , ras and cas are low). dq0 - dq31 data input/output data input for program/erase. data output for read. vcc/vss power supply/ground power and ground for the input buffers and the core logic. vccq/vssq data output power/ground power and ground for the output buffers. word x32/x16 mode selection double word mode/word mode, depending on polarity of word pin (word = high, double word mode; word = low, word mode). should be set to the desired state during power-up and prior to any device operation. dqm data-out masking masks output operation when a complete burst is not required. nc no connection not connected we write enable enables the chip to be written. vpp program/erase pin supply program/erase power supply.
4 at49ld3200(b) 1940b ? 11/01 functional block diagram absolute maximum ratings* temperature under bias ................................ -55 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground .....................................-0.6v to +4.6v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on v pp with respect to ground ...................................-0.6v to +13.5v power dissipation .............................................................. 1 w timing register programming register latency & burst length column decoder 1m x 32 cell array io buffer program/ erase logic we vpp clk clk add dq15 cs cas ras mr dq16 dq0 cke lras lras lcke lcas lmr dq31 dqm address register row buffer row decoder sense amp column buffer 8k x 16 boot block add
5 at49ld3200(b) 1940b ? 11/01 notes: 1. v ih (max) = 4.6v for pulse width < 10 ns acceptable, pulse width measured at 50% of pulse amplitude. 2. v il (min) = -1.5v for pulse width < 10 ns acceptable, pulse width measured at 50% of pulse amplitude. note: 1. if clk transition time is longer than 1 ns, timing parameters should be compensated. add [(t r + t f )/2-1] ns for transition time longer than 1 ns. transition time is measured between v il (max) and v ih (min). dc and ac operating range at49ld3200(b)-10 at49ld3200(b)-13 at49ld3200(b)-20 operating temperature (case) commercial 0 c - 70 c0 c - 70 c0 c - 70 c industrial -40 c - 85 c-40 c - 85 c-40 c - 85 c v cc , v ccq power supply 3.0v to 3.6v 3.0v to 3.6v 3.0v to 3.6v dc characteristics symbol parameter condition min max units i sb1 v cc standby current cmos cke = 0, t cc = min 20 ma i sb2 v cc standby current ttl cke = v il (max), t cc = min 20 ma i sb3 v cc active standby current cs v ih (min), t cc = min 50 ma i cc v cc active current t cc = min, all outputs open 150 ma i il input leakage current 0v v in v dd + 0.3v pins not under test = 0v -10 10 a i ol output leakage current (io out disabled) (0v v out v dd max) all outputs in high-z -10 10 a v ih input high voltage, all inputs note (1) 2.0 v dd + 0.3 v v il input low voltage, all inputs note (2) -0.3 0.8 v v oh output high voltage level (logic 1) i oh = -2 ma 2.4 v v ol output low voltage level (logic 0) i ol = 2 ma 0.4 v ac operating test conditions t a = 0 to 70 c, v cc = 3.3v 0.3v, unless otherwise noted. parameter (1) value timing reference levels of input/output signals 1.4v input signal levels v ih /v il = 2.4v/0.4v transition time (rise & fall) of input signals t r /t f = 1 ns/1 ns output load lv t t l
6 at49ld3200(b) 1940b ? 11/01 figure 1. dc output load circuit figure 2. ac output load circuit notes: 1. this parameter is characterized and is not 100% tested. 2. v pp behaves as an output pin. pin capacitance (1) f = 1 mhz, t = 25 c symbol typ max units conditions c in 46pfv in = 0v c out (2) 812pfv out = 0v 3.3v 1200 w 870 w output 50 pf v oh ( dc ) = 2.4v, i oh = -2 ma v ol ( dc ) = 0.4v, i ol = 2 ma vtt = 1.4v 50 w output 50pf z 0 = 50 w
7 at49ld3200(b) 1940b ? 11/01 notes: 1. these t rc values are for bl = 8. for bl = 4, t rc = 7 clks for up to 100 mhz, t rc = 6 clks for up to 75 mhz, t rc = 5 clks for up to 50 mhz. ras latency increase means a simultaneous t rc increase in the same number of cycles. (if ras latency is 3clks, t rc is 12 clks for bl = 8.) refer to page 27 for gapless operation. 2. these t vcvc values are for bl = 8. for bl = 4, t vcvc = 5 clks for up to 100 mhz, t vcvc = 4 clks for up to 75 mhz, t vcvc = 3 clks for up to 50 mhz. refer to page 27 for gapless operation. ac read characteristics ac operating conditions unless otherwise noted. symbol parameter < 100 mhz < 75 mhz < 50 mhz units min max min max min max t cc clk cycle time 10 13 20 ns t sac clk to valid output delay 7 8 9 ns t oh data output hold time 3 4 4 ns t ch clk high pulse width 3 4 6.5 ns t cl clk low pulse width 3 4 6.5 ns t rc row-active to row-active (1) 11 10 9 clks t ss input setup time 2 4 4 ns t sh input hold time 1 2 2 ns t slz clk to output in low-z 0 0 0 ns t shz clk to output in high-z 7 10 15 ns t t transition time 0.1 10 0.1 10 0.1 10 ns t vcvc valid cas enable to valid cas enable (2) 9 8 7 clks
8 at49ld3200(b) 1940b ? 11/01 notes: 1. a 0 ~ a 6 : program keys (@mrs). after power-up, mode register set can be set before issuing other input command. after the mode register set command is completed, no new commands can be issued for 3 clk cycles, and cs or mr state must be defined ? h ? within 3 clk cycles. refer to the mode register control table. 2. in the case cke is low, two standby modes are possible. those are standby mode in power-down, and active standby mode in clock suspend (non-power-down). power-down: cke = ? l ? (after no command is issued for 60 s) clock suspend: cke = ? l ? (at the range of row active, read and data out) 3. dqm sampled at rising edge of a clk makes a high-z state the data-out state, delayed by 2 clk cycles. 4. precharge command on synch. dram can be used for burst stop operation during burst read operation only. 5. mode selection is controlled by the polarity of word pin, ? h ? state is dwm, ? l ? state is wm. word should be set to the desired state during power-up and prior to any device operation. 6. data is provided through dq 0 ~ dq 31 . refer to ac programming and erasing waveforms. 7. dq 0 ~ dq 31 will output manufacturer code/device code. 8. a 0 = a 2 = a 11 = ? h ? , a 1 = a 10 = a 12 = ? l ? 9. the user can tie mr and we together to simplify the interface of the at49ld3200(b) onto the standard sdram bus. function truth table (v = valid, x = don ? t care, h = logic high, l = logic low) abbreviations (ra: row address, ca: column address, nop: no operation command, dwm: double word mode, wm: word mode) command cken-1 cken cs ras cas mr (9) dqm add. word vpp we register (1) mode register set h x l l l l x code x x x row active row access & latch hxllhhxraxxx read column access & latch hxlhlhxcaxxh burst stop hxlhhlxxxxx (precharge on synch. dram) hxllhlxxxxx power-down and clock suspend (2) tw o standby mode entry h l x x x x x x x x x exit l h x x x x x x x x x dqm (3) hxxxxxvxxxx no operation command (4) hxhxxxxxxxx hxlhhhxxxxx organization control (5) hxlhlhxca h xh l program/erase (6) hxlhlxxcaxxl fast program/erase (6) hxlhlxxcax12vl program/erase inhibit h x h x x x x x x x x product identification (7) mode register set h x l l l l x a 7 = h x x x read h x l h l h x l x x h continuity test mode entry h x l h l x x ca x x l exit x x x x x x x code (8) xxx
9 at49ld3200(b) 1940b ? 11/01 notes: 1. program/erase is performed through the synchronous bus cycle operation after the boot block is activated through either power-up or mode register set. 2. it is recommended to hold cke low if clk is running during asynchronous boot block mode except for synchronous com- mand cycle and mrs operations. note: 1. after power-up, when the user wants to change mode register set, the user must exit from power-down mode and start mode register set before entering normal operation mode. reserved modes are not to be used; device function in these modes is not guaranteed. asynchronous boot block function truth table command clk (2) cke (2) cs ras cas mr dqm add. word vpp we read x x l x x x l add x x x output disable xxlxxxhxxxx program/erase (1) hlhlxxaddx xl fast program/erase (1) hlhlxxaddx12vl program/erase inhibit h h x x x x x x x x mode register control table (1) register programmed with mrs address a7 a6 a5 a4 a3 a2 a1 a0 function product id ras latency cas latency burst type burst length product id ras latency cas latency burst type burst length a7 ? read ? a6 type a5 a4 a3 length a2 type a1 a0 length 0 array 0 1 0 0 0 reserved 0 sequential 0 0 reserved 1 id 1 2 001 2 1 interleave 0 1 4 010 3 1 0 8 011 4 1 1 boot block 100 5 101 6 110 7 111 8
10 at49ld3200(b) 1940b ? 11/01 addressing map note: 1. column address msb (at x32 organization) (x = don ? t care) note: 1. column address msb (at x16 organization) (x = don ? t care) notes: 1. for x16 operation, when ca 0 is set to low, data belonging to 0 ~ 15th registers are output to dq 0 ~ dq 15 pins, and when ca 0 is set to high, data belonging to 16 ~ 31th registers are output to dq 0 ~ dq 15 pins. 2. asynchronous boot block uses x16 operation and a 0 ~ a 12 as address inputs. word = ? h ? : x32 organization (1) function a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 row address ra 0 ra 1 ra 2 ra 3 ra 4 ra 5 ra 6 ra 7 ra 8 ra 9 ra 10 ra 11 ra 12 column address ca 0 ca 1 ca 2 ca 3 ca 4 ca 5 ca 6 (1) xxxxxx word = ? l ? : x16 organization (1) function a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 row address ra 0 ra 1 ra 2 ra 3 ra 4 ra 5 ra 6 ra 7 ra 8 ra 9 ra 10 ra 11 ra 12 column address ca 0 ca 1 ca 2 ca 3 ca 4 ca 5 ca 6 ca 7 (1) xxxxx each address is arranged as follows (1)(2) for x32 operation, msb lsb address register ar 19 ar 18 ar 17 ... ar 8 ar 7 ar 6 ... ar 3 ar 2 ar 1 ar 0 address ra 12 ra 11 ra 10 ... ra 1 ra 0 ca 6 ... ca 3 ca 2 ca 1 ca 0 bl = 8 bl = 4 * initial address
11 at49ld3200(b) 1940b ? 11/01 device operations clock (clk) a square wave signal (clk) must be applied externally at cycle time t cc . all operations are synchronized to the rising edge of the clock. the clock transitions must be mono- tonic between v il and v ih . during operation with cke high, all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around the positive edge of the clock for proper functionality and i cc specifications. clock enable (cke) the clock enable (cke) gates the clock into the at49ld3200(b) and is asserted high during all cycles, except for power-down, standby and clock suspend mode. if cke goes low synchronously with clock (setup and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen for as long as the cke remains low. all other inputs are ignored from the next clock cycle after cke goes low. the at49ld3200(b) remains in the power-down mode, ignoring other inputs for as long as cke remains low. the power-down exit is synchro- nous as the internal clock is suspended. when cke goes high at least ? 1 clk + t ss ? before the rising edge of the clock, then the at49ld3200 becomes active from the same clock edge accepting all the input commands. nop and device deselect when ras , cas and mr are high, the at49ld3200(b) performs no operation (nop). nop does not initiate any new operation. device deselect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas , mr burst sequence (burst length = 4) initial address sequential interleave a1 a0 0001230123 0112301032 1023012301 1130123210 burst sequence (burst length = 8) initial address sequential interleave a2 a1 a0 0 0 0 0123456701234567 0 0 1 1234567010325476 0 1 0 2345670123016745 0 1 1 3456701232107654 1 0 0 4567012345670123 1 0 1 5670123454761032 1 1 0 6701234567452301 1 1 1 7012345676543210
12 at49ld3200(b) 1940b ? 11/01 and all the address inputs are ignored. in addition, entering a mode register set com- mand in the middle of a normal operation results in an illegal state in the at49ld3200(b). power-up the following power-up sequence is recommended. 1. apply power and start clock. hold the mr , cke and dqm inputs high; all other pins are a nop condition at the inputs before or along with v cc (and v ccq ) supply. 2. set word to the desired state (prior to any device operation). 3. to change the default mode register set values, perform a mode register set cycle to program the ras latency, cas latency, burst length and burst type. 4. at the end of three clock cycles after the mode register set cycle, the device is ready for operation. when the above sequence is used for power-up, all outputs will be in high impedance state. the high impedance of outputs is not guaranteed in any other power-up sequence. for at49ld3200b, asynchronous boot block will be selected after power-up. mode selection control mode selection is controlled by the polarity of word pin. word should be set to the desired state during power-up and prior to any device operation. the at49ld3200(b) can be organized as either double word wide (x32) or word wide (x16). the organization is selected via the word pin. when word is asserted high (v ih ), the double word- wide organization is selected. when word is asserted low (v il ), the word-wide organi- zation is selected. address decoding the address bits required to decode one of the available cell locations out of the total depth are multiplexed onto the address select pins and latched by externally applying two commands. the first command, ras asserted low, latches the row address into the device. a second command, cas asserted low, subsequently latches the column address. mode register set (mrs) the mode register stores the data for controlling the various operating modes of at49ld3200(b). it programs the ras latency, cas latency, burst length, burst type, selects product id read or activates the asynchronous boot block. for at49ld3200(b), the default value of the mode register is defined as array read with ras latency = 2, cas latency = 5, burst length = 4, sequential burst type. when and if the user wants to change its values, the user must exit from power-down mode and start mode register set before entering normal operation mode. the mode register is repro- grammed by asserting low on cs , ras , cas and mr (the at49ld3200(b) should be in active mode with cke already high prior to writing the mode register). the state of address pins a 0 ~ a 7 in the same cycle as cs , ras , cas and mr going low is the data written in the mode register. three clock cycles are required to complete the program in the mode register, therefore after a mode register set command is completed, no new commands can be issued for 3 clock cycles and cs or mr must be high within 3 clock cycles. the mode register is divided into various fields, depending on functionality. the burst length field uses a 0 ~ a 1 , burst type uses a 2 , cas latency (read latency from col- umn address) uses a 3 ~ a 5 , ras latency uses a 6 (ras to cas delay), array read or product id read uses a7. refer to mode register control table for specific codes for various burst lengths, burst types, cas latencies, ras latencies, and read modes.
13 at49ld3200(b) 1940b ? 11/01 latency there are latencies between the issuance of a row active command and when data is available on the i/o buffers. the ras to cas delay is defined as the ras latency. the cas to data out delay is the cas latency. the cas and ras latencies are programma- ble through the mode register. ras latencies of 1 and 2, and cas latencies of 2 through 6 are supported. it is understood that some ras and cas latency values are reserved for future use, and are not available in this generation of synchronous flash. the follow- ing are the supported minimum values: ras latency = 2, and cas latency = 6 for 100 mhz operation, and ras latency = 2, and cas latency = 5 for 66 mhz operation, and ras latency = 1, and cas latency = 4 for 50 mhz operation, and ras latency = 1, and cas latency = 3 for 33 mhz operation. dqm operation the dqm is used to mask output operations when a complete burst read is not required. it works similar to oe during a read operation. the read latency is two cycles from dqm, which means dqm masking occurs two cycles later in the read cycle. dqm operation is synchronous with the clock. the masking occurs for a complete cycle. (also refer to the dqm timing diagram.) burst read the burst read command is used to access a burst of data on consecutive clock cycles from an active row state. the burst read command is issued by asserting low cs and cas with mr being high on the rising edge of the clock. the first output appears in cas latency number of clock cycles after the issuance of the burst read command. the burst length, burst sequence and latency from the burst read command are determined by the mode register, which is already programmed. burst read can be initiated on any column address of the active row. the output goes into high-impedance at the end of the burst, unless a new burst read is initiated to keep the data output gapless. the burst read can be terminated by issuing another burst read. sector erase before a word/double word can be reprogrammed, it must be erased. the erased state of the memory bits is a logical ? 1 ? . the at49ld3200(b) is organized into eight uniform four megabit sectors (sa0 - sa7) that can be individually erased. the sector erase command is a synchronous six-bus cycle operation (refer to the command definition table and program cycle and erase cycle waveforms). the erase code consists of 6- byte (dq8 - dq31 are don ? t care inputs for the command) load commands to specific address locations with a specific data pattern. the sector address and 30h data input are latched in the sixth cycle. the sector erase starts at the following rising edge of clk after the sixth cycle. the erase operation is internally controlled; it will automatically time to completion. any commands written to the device during the erase cycle will be ignored. the maxi- mum time needed to erase one sector is t ec . word/double word programming once a sector is erased, it is programmed (to a logical ? 0 ? ) on a word-by-word/double- word-by-double-word basis. programming is accomplished via the internal device com- mand register and is synchronous four-bus cycle operation (refer to the command definition table and program cycle and erase cycle waveforms). the programming operation starts at the following rising edge of clk after the fourth cycle. the device will automatically generate the required internal program pulses. any commands written to the device during the embedded programming cycle will be ignored. please note that a data ? 0 ? cannot be programmed back to a ? 1 ? ; only erase operations can convert ? 0 ? s to ? 1 ? s. programming is completed after the specified t pgm cycle time. the data polling feature may also be used to indicate the end of a program cycle.
14 at49ld3200(b) 1940b ? 11/01 product identification the product identification mode identifies the device and manufacturer as atmel. this mode can be used by an on-board controller or external programmer to identify the cor- rect programming algorithm for the atmel product. data polling the at49ld3200(b) features data polling to indicate the end of a program or sector erase cycle. data polling may begin at any time during the program or sector erase cycle. during a program cycle, an attempted read of the last word/double word loaded will result in the complement of the loaded data in dq7. once the program cycle has com- pleted, true valid data can be read on all outputs and the next cycle may begin. during a sector erase operation, an attempt to read the device will give a ? 0 ? on dq7. once the sector erase cycle has completed, logical ? 1 ? data can be read on all outputs from the device. hardware data protection hardware features protect against inadvertent programming or erasure to the at49ld3200(b) in the following way: v cc sense: if v cc is below 2.3v (typical), the pro- gram or erase function is inhibited; but if v cc dips below 2.3v during program or erase cycle, the respective function will be interrupted and the data at the location being pro- grammed may be corrupted. continuity test mode the at49ld3200(b) has built-in circuitries to make input and output pin continuity check simple and easy. this mode can be activated via the internal device command register and is a synchronous five-bus cycle operation (refer to the command definition table and continuity test mode entry waveforms). after the bus cycle operation, keep dqm high (v ih ) and allow 5 sec for circuit setup time or until data is no longer asserted at dq0 - dq7, whichever takes longer. this will keep dq0 - dq7 from contention since data is asserted at dq0 - dq7 during the mode entry sequence. then dqm can be asserted low (v il ) to enable dq0 - dq7 for test. once in this asynchronous mode, input pins are virtually tied to output pins internally forming input - output pin pairs. the output pin of the pair will follow the logic state of the input pin of the pair (refer to the input - output pin pairs table). to exit the mode, a 0 , a 2 and a ii are asserted high (v ih ) and a 1 , a 10 and a 12 are asserted low (v il ), allow 5 sec for circuit recovery time before returning the device for normal operation.
15 at49ld3200(b) 1940b ? 11/01 asynchronous boot block the at49ld3200b will automatically activate the asynchronous boot block after power-up and the at49ld3200 can activate the asynchronous boot block through the mode register set. the size of the boot block is 8k x 16 bits with addresses a 0 ~ a 12 and outputs dq 0 ~ dq 15 . the contents of the boot block are accessed asynchronously, meaning the data at outputs will change according to the address inputs after t acc , with- out any external clocking signals. programs and erases are performed using the synchronous bus cycle operation (refer to command definitions table and program cycle and erase cycle waveforms) after the boot block is activated either through power-up or mode register set. programming of the boot block is set up for x16 mode. this asynchronous boot block has a lockout feature that prevents programming or erasing of data in this boot block once the feature has been enabled. this feature does not have to be activated; the boot block ? s usage as a protected region is optional to the user. once this feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 3.6v or less are used. to activate the lockout feature, input - output pin pairs input output mr dq0, dq16 ras dq1, dq17 cas dq2 dqm dq18 cs dq3 word dq19 a12 dq4 a11 dq20 a10 dq5 a0 dq21 a1 dq6, dq22 a2 dq7, dq23 a3 dq8, dq24 a4 dq9, dq25 a5 dq10 a6 dq26 a7 dq11 a8 dq27 a9 dq12 cke dq28 clk dq13, dq29 we dq14, dq30 vpp dq15, dq31
16 at49ld3200(b) 1940b ? 11/01 boot block lockout command, which is a synchronous five-bus cycle operation, must be performed (refer to command definitions table and program cycle waveforms). a software method is available to determine if programming or erasing of the boot block is locked out. issue boot block lockout verify command and observe dq 0 ~ dq 7 . if the data show 00h/02h, the boot block can be programmed or erased; if the data show 01h/03h, the lockout feature has been enabled and the boot block cannot be pro- grammed or erased. the boot block lockout verify exit command should be used to return to standard operation (refer to command definition table and boot block lockout verify waveforms). the user can override the boot block lockout by taking the mr pin to 12 volts after the boot block is activated. when the mr pin is brought back to ttl levels, the boot block lockout feature is again active.
17 at49ld3200(b) 1940b ? 11/01 notes: 1. the data format in each bus cycle is as follows: dq31 - dq8 (don ? t care); dq7 - dq0 (hex). 2. sa = sector addresses: any word/double word address within a sector can be used to designate the sector address. see sector address mapping table below. 3. allow minimum 200 ns after boot block lockout verify command and before read. 4. allow minimum 10 s after boot block lockout verify exit command for the device to return to standard operation. command definition in hex (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle ra ca data ra ca data ra ca data ra ca data ra ca data ra ca data word/ double word program 4 aa55aa552a55aa55a0racad in sector erase 6 aa55aa552a55aa55 80aa55aa552a55sa (2) x30 continuity test mode entry 5 aa55aa552a55aa55 80aa55aaaa55 70 boot block lockout 5 aa55aa552a55aa55 80aa55aaaa55 40 boot block lockout verify 5 aa55aa552a55aa55 80aa55aaaa55 90 boot block lockout verify exit 5 aa55aa552a55aa55 80aa55aaaa55f0 sector address mapping sector size (word/double word) x16 address range x32 address range ca 7-0 ra 12-0 ca 6-0 ra 12-0 sa0 256k/128k x 00xx 03xx x 00xx 03xx sa1 256k/128k x 04xx 07xx x 04xx 07xx sa2 256k/128k x 08xx 0bxx x 08xx 0bxx sa3 256k/128k x 0cxx 0fxx x 0cxx 0fxx sa4 256k/128k x 10xx 13xx x 10xx 13xx sa5 256k/128k x 14xx 17xx x 14xx 17xx sa6 256k/128k x 18xx 1bxx x 18xx 1bxx sa7 256k/128k x 1cxx 1fxx x 1cxx 1fxx
18 at49ld3200(b) 1940b ? 11/01 basic feature and function descriptions mrs clock suspend clock suspend exit and power-down exit note: after mode register set command is completed, no new commands can be issued for 3 clock cycles, and mr or cs should be fixed ? h ? within a minimum of 3 clock cycles. mode re g ister set clk cmd mrs act ( 1 ) 3clk d 0 internal clk clock suspended durin g burst read ( bl=4 ) masked by cke dq 0 dq 1 dq 2 dq 3 suspended dout clk cmd rd cke data : this command cannot be activated. internal clk cke internal clk 1 ) clock suspend exit clk cke cmd rd 2 ) power down clk cmd nop act t ss t ss
19 at49ld3200(b) 1940b ? 11/01 dqm operation note: dqm makes data out high-z after 2 clks, which should be masked by cke ? l ? . dq 0 dq 1 dq 3 dq 0 dq 2 dq 3 dq 1 dq 2 dq 3 masked by dqm dq 0 d 1 dq 1 dq 3 dq 0 dq 7 dq 2 dq 6 dq 7 dq 1 dq 7 dq 6 dq 5 clk cmd dqm data ( cl2 ) data ( cl3 ) data ( cl4 ) rd clk cmd dqm cke rd 1 ) read mask ( bl=4 ) 2 ) dqm with clock suspended ( bl=8 ) high-z high-z high-z dq 5 dq 4 dq 3 high-z high-z high-z high-z high-z high-z dqm to data-out mask = 2clks high-z high-z high-z ( 1 ) data ( cl2 ) data ( cl3 ) data ( cl4 )
20 at49ld3200(b) 1940b ? 11/01 read cycle i: normal @ras latency = 2, cas latency = 5, burst length = 4 note: when the burst length is 4 at 66 mhz, t rc is equal to 6 clock cycles. 0 1 2 3 4 5 6 7 8 9 10111213141516171819 t ss t sh cke cs ras cas addr data t ch t cc t cl t rc high tsh t ss t shz t sac t oh dqa0 dqa1 dqa2 dqa3 cab rab ras latenc y mr ( 1 ) t rc =6 clocks at bl=4 row active read row active read : don't care t ss t sh dqb0 dqb1 dqb2 dqb3 caa raa clk
21 at49ld3200(b) 1940b ? 11/01 read cycle ii: consecutive column access @ras latency = 2, cas latency = 5, burst length = 4 note: when column access is initiated beyond t vcvc , at bl = 4, ca a access read is completed, ca b access read begins. 0 1 2 3 4 5 6 7 8 9 10111213141516171819 t ss t sh t ss t sh cke cs ras cas addr data t ch t cc t cl high t sh t ss caa raa t shz t sac t oh dqb1 dqb2 dqb3 cab dqb0 ras latenc y t vcvc =4 clocks at bl=4 burst len g th=4 dqa1 dqa2 dqa3 dqa0 mr row active read read : don't care clk
22 at49ld3200(b) 1940b ? 11/01 read cycle iii: clock suspend @ras latency = 2, cas latency = 5, burst length = 4 notes: 1. from next clock after cke goes low, clock suspension begins. 2. for clock suspension, data output state is held and maintained. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t ss t sh cke cs ras cas addr data t ch t cc t cl t sh t ss caa raa ras latenc y t vcvc = 4 clocks at bl=4 ( 2 ) burst len g th=4 dqa2 dqa3 dqa0 ( 1 ) mr row active read clock suspend resume : don't care dqa1 clk internal clk
23 at49ld3200(b) 1940b ? 11/01 read interrupted by precharge command and burst read stop cycle @burst length = 8 notes: 1. the burst stop command is valid at every page burst length. the data bus goes to high-z after the cas latency from the burst stop command is issued. 2. the interval between read command (column address presented) and burst stop command is 1 cycle (min). 0 1 2 3 4 5 6 7 8 9 10111213141516171819 high cl=3 addr cas ras cs cke clk mr dqm dqa0 dqa1 dqa2 dqa4 dqb0 dqb1 dqb2 dqb3 dqb4 dqb5 raa caa cab row active prechar g e burst stop read read : don't care (1) cl=2 data dqa0 dqa1 dqa2 dqa4 dqb0 dqb1 dqb2 dqb3 dqb4 dqb5 dqa3 dqa3 (1)(2) (1) (2) (2)
24 at49ld3200(b) 1940b ? 11/01 power-down and clock suspend cycle: @ras latency = 2, cas latency = 5, burst length = 4 notes: 1. from next clock after cke goes low, clock suspend and power-down begins. 2. after power-down exit, nop should be issued and new command can be issued after 1 clock. 3. clock suspend is in active standby mode. 012345678910111213141516171819 cke cs ras cas addr data read caa raa dqa1 dqa2 dqa0 mr dqa3 row active ( hi g h ) clk (internal) nop power-down clock suspend entr y entr y power-down exit clock suspend exit : don't care t ss t sh ( 2 ) ( 1 ) t ss ( 1 ) ( 3 ) clock sus p end power down data hi g h-z state
25 at49ld3200(b) 1940b ? 11/01 mode register set: @ras latency = 2, cas latency = 5, burst length = 4 notes: 1. after the mode register set is completed, no new commands can be issued for 3 clk cycles. 2. after power-up, necessarily mode register set should be completed at least one time and cs or mr must be fixed ? h ? within 3 clock cycles, and when user wants to change mode register set, user must exit from power-down mode and start mode register set before chip enters normal operation mode. 012345678910111213141516171819 t ss t sh cke cs ras cas addr data mr t ch t cc t cl high code raa data high-z state mrs row active : don't care caa dqa0 dqa1 dqa2 dqa3 clk
26 at49ld3200(b) 1940b ? 11/01 note: 1. after the power-up, when user wants to change mr set, user must exit from power-down mode and start mr set before chip enters normal operation mode. detailed functional truth table current state input signal next state operation cke cs ras cas mr add. after power-up (1) lxxxxxpower-down h l l h h ra row active; latch ra hllllcodemode register set row active hllhhra if consecutive row access is issued within t rc (min.) without cas enabling, only the final ra is valid. h l h l h ca begin read; latch ca hllllcodeillegal (1) l xxxxxclock suspend read hllhhra row access in read state, within the t rc , previous read is ignored and new row is activated. beyond the t rc , previous read is completed and new read begins. hlhlhca consecutive column access, within the t vcvc , only the final ca is valid and the previous burst read is ignored. beyond the t vcvc , the previous read is completed and new read begins. h l l h l x nop (after burst read)/read interrupt h l h h l x nop (after burst read)/read interrupt hllllcodeillegal (1) lxxxxxclock suspend/power-down any statellllhxlow power consumption mode any state h l h h h x nop any state hlllhxillegal h l h l l ca illegal
27 at49ld3200(b) 1940b ? 11/01 technical notes frequency vs. ac parameter relationship table (1) notes: 1. above tables are not specifications values, but rather the actual number of clock cycles. there are no gapless operatio ns for cas latency 7 and 8. 2. minimum clocks for gapless operation. 3. t rc (max) = t vcvc (max) = 50 s. if t rc (max) or t vcvc (max) has been reached, a new ? active ? command is necessary for new access. < 100 mhz burst length ras latency cas latency t rc (min) t vcvc (min) 42 675 (2) 786 82 6119 (2) 71210 < 75 mhz burst length ras latency cas latency t rc (min) t vcvc (min) 42 564 (2) 675 82 5108 (2) 6119 < 50 mhz burst length ras latency cas latency t rc (min) t vcvc (min) 41 44 (2) 3/4 (2) 554 (2) 665 81 48 (2) 7/8 (2) 598 (2) 6109
28 at49ld3200(b) 1940b ? 11/01 cas interrupt notes: 1. by ? interrupt ? , it is meant to stop burst read by external command before the end of burst. by ? cas interrupt ? , to stop burst read by cas access. 2. cas to cas delay (=1 clk). read interrupt operation by issuing the precharge of burst stop command notes: 1. the data bus goes to high-z after cas latency from the burst stop (or precharge) command. 2. valid output data will last up to cl-1 clock cycle from pre command. dqb 1 dqb 2 rd dqb 3 rd a b dqb 0 dqb 1 dqb 2 dqb 3 dqb 0 dqb 1 dqb 2 dqb 3 dqb 0 ( 2 ) data ( cl2 ) data ( cl3 ) data ( cl4 ) read interrupted b y read ( bl=4 ) (1) clk cmd add rd pre dq 0 dq 0 dq 1 dq 0 dq 1 rd stop dq 0 dq 1 dq 0 dq 1 dq 0 dq 1 dq 1 clk cmd clk cmd case i ) issued read interru p t command durin g burst read o p eration p eriod. rd pre dq 0 dq 0 dq 0 ( 2 ) rd stop dq 0 dq 0 dq 0 clk cmd clk cmd case ii ) issued read interru p t command between read command and data out. ( 2 ) ( 1 ) ( 1 ) data ( cl2 ) data ( cl3 ) data ( cl4 ) data ( cl2 ) data ( cl3 ) data ( cl4 ) data ( cl2 ) data ( cl3 ) data ( cl4 ) data ( cl2 ) data ( cl3 ) data ( cl4 )
29 at49ld3200(b) 1940b ? 11/01 read cycle depending on t rc @rl = 2, cl = 6, bl = 4; 100 mhz @rl = 2, cl = 5, bl = 4; 75 mhz @rl = 1, cl = 4, bl = 4; 50 mhz rda trc(min)=7 act tcc=10ns clk cmd case i ) case ii ) case iii ) rdb act rdb dqb 1 dqb 2 dqb 0 dqb 1 dqb 2 dqb 3 dqb 0 dqa 1 dqa 2 dqa 0 dqa 3 dqa 1 dqa 2 dqa 0 dqa 3 high-z case i ) rdb act case ii ) case iii ) act dqb 1 dqb 2 dqb 3 dqb 0 dqb 3 rda trc(min)=6 act tcc=15ns rdb act rdb dqb 1 dqb 2 dqb 3 dqb 0 dqb 1 dqb 2 dqb 3 dqb 0 dqa 1 dqa 2 dqa 0 dqa 3 dqa 1 dqa 2 dqa 0 dqa 3 high-z case i ) rdb act case ii ) case iii ) act dqb 1 dqb 2 dqb 3 dqb 0 clk cmd case i ) case ii ) case iii ) trc(min)=4 act tcc=20ns act dqb 1 dqb 2 dqb 3 dqb 0 dqb 1 dqb 2 dqb 3 dqb 0 dqa 1 dqa 2 dqa 0 dqa 3 dqa 1 dqa 2 dqa 0 dqa 3 case i ) act case ii) case iii) act dqb 1 dqb 2 dqb 3 dqb 0 clk cmd case i ) case ii ) case iii ) rda rdb rdb rdb (gapless operation)
30 at49ld3200(b) 1940b ? 11/01 read cycle depending on t vcvc @rl = 2, cl = 6, bl = 4; 100 mhz @rl = 2, cl = 5, bl = 4; 75 mhz @rl = 1, cl = 4, bl = 4; 50 mhz tvcvc=5 act clk cmd case i ) case ii ) case iii ) rda dqb 1 dqb 2 dqb 3 dqb 0 case i) case ii) case iii) dqb 1 dqb 2 dqb 3 dqb 0 dqb 1 dqb 2 dqb 3 dqb 0 dqa 0 dqa 1 dqa 0 rdb rdb rdb dqa 2 dqa 3 dqa 1 (gapless operation) dqa 3 dqa 2 tcc=10ns tvcvc=4 act dqb 1 dqb 2 dqb 3 dqb 0 case i) case ii) case iii) clk cmd case i ) case ii ) case iii ) dqb 1 dqb 2 dqb 3 dqb 0 dqb 1 dqb 2 dqb 3 dqb 0 dqa 0 dqa 1 dqa 0 rda rdb rdb rdb dqa 2 dqa 3 dqa 1 (gapless operation) dqa 3 dqa 2 tcc=15ns tvcvc=3 act dqb 1 dqb 2 dqb 3 dqb 0 case i) case ii) case iii) clk cmd case i ) case ii ) case iii ) dqb 1 dqb 2 dqb 3 dqb 1 dqb 2 dqb 3 dqb 0 dqa 0 dqa 1 dqa 0 rda rdb rdb rdb dqa 3 dqa 2 (gapless operation) : invalid data dqa 2 dqa 1 tcc=20ns
31 at49ld3200(b) 1940b ? 11/01 ac waveforms for boot block read operation ac characteristics for boot block read operation symbol parameter condition min max units t acc address to output delay cs = dqm = v il 170 ns t oe dqm to output delay cs = v il 60 ns t df dqm high to output float 40 ns t oh output hold from address 0 ns address valid t acc t df t oh high-z output valid t oe address dqm output cs
32 at49ld3200(b) 1940b ? 11/01 l program cycle waveforms sector erase cycle waveforms notes: 1. the precharge command is optional. a precharge command (cs , ras , mr = l) during program and sector erase cycles (we = l) will be treated as nop, and the number of clock cycles between the bus cycle and the precharge command or vice versa should be ? don ? t care ? . 2. for boot block programming, ra = ca = a 0 ~ a 12 and be held valid throughout program cycle; dqm should be held ? h ? dur- ing the four-bus cycle command operation. 3. for boot block erasing, sa = x; dqm should be held ? h ? during the six-bus cycle command operation. 3-volt program and erase cycle characteristics symbol parameter typ max units t pgm word/double word programming time 50 600 s t ec sector/boot block erase cycle time 2.0/300 seconds/ms t bbl boot block lockout enable time 10 ms i cc2 v cc current during program and erase cycle 150 ma high-speed 12-volt program and erase cycle characteristics symbol parameter typ max units t pgm word/double word programming time 15 200 s t ec sector/boot block erase cycle time 1.2/200 seconds/ms i cc3 v cc current during program and erase cycle 75 ma i pp3 v pp current during program and erase cycle 75 ma cs program cycle clk we ras cas aa 55 55 2a aa 55 ra ca data aa 55 a0 d in addr precharge command t pgm precharge command precharge command precharge command cs sector erase cycle clk we ras cas aa 55 55 2a aa 55 data aa 55 80 aa addr t ec precharge command aa 55 55 2a sa x 55 30 precharge command precharge command precharge command precharge command precharge command
33 at49ld3200(b) 1940b ? 11/01 data polling waveforms note: during program cycle, data = complement of loaded dq7. after program cycle, data = same state as loaded dq7. during sector erase cycle, data = ? 0 ? ; after sector erase cycle, data = ? 1 ? . data polling waveforms for boot block note: during program cycle, data = complement of loaded dq7. after program cycle, data = same state as loaded dq7. during sector erase cycle, data = ? 0 ? ; after sector erase cycle, data = ? 1 ? . dqm cs t pgm /t ec clk we ras cas dq7 (rl2, cl5, bl4) data addr read read (data polling) ra ca data ra ca dqm cs t pgm /t ec clk we ras cas dq7 (rl2, cl5, bl4) data addr read read (data polling) data valid address
34 at49ld3200(b) 1940b ? 11/01 product id cycle waveforms note: for x16 mode, manufacturer code, mc = 001f(hex), device code, dc = 32c2 (hex). for x32 mode, code, c = 32c2001f (hex). continuity test mode entry waveforms dqm cs product id cycle clk we ras cas data (cl5, bl4, x16) addr read a7 mr mrs dc mc data (cl5, bl4, x32) c clk cs we ras cas addr aa 55 55 2a aa 55 aa 55 55 aa data aa 55 80 aa 70 precharge command precharge command precharge command precharge command dqm
35 at49ld3200(b) 1940b ? 11/01 boot block lockout cycle waveforms boot block lockout verify cycle waveforms note: dq = xx00 (hex) implies boot block not activated and lockout not enabled. dq = xx01 (hex) implies boot block not activated and lockout enabled. dq = xx02 (hex) implies boot block activated and lockout not enabled. dq = xx03 (hex) implies boot block activated and lockout enabled. cs boot block lockout cycle clk we ras cas aa 55 55 2a aa 55 data aa 55 80 aa addr t bbl aa 55 aa 55 40 precharge command precharge command precharge command precharge command precharge command cs boot block lockout verify cycle clk we ras cas aa 55 55 2a aa 55 data (cl5, bl4) aa 55 80 aa addr 200 ns aa 55 55 aa 90 precharge command read precharge command precharge command precharge command precharge command dq
36 at49ld3200(b) 1940b ? 11/01 boot block lockout verify exit cycle waveforms cs boot block lockout verify exit cycle clk we ras cas aa 55 55 2a aa 55 data aa 55 80 aa addr aa 55 aa 55 f0 precharge command precharge command precharge command precharge command precharge command 10 s
37 at49ld3200(b) 1940b ? 11/01 ordering information max freq (mhz) i cc (ma) ordering code package operation range active standby 100 150 0.05 at49ld3200-10tc 86t commercial (0 to 70 c) 150 0.05 at49ld3200-10ti 86t industrial (-40 to 85 c) 75 150 0.05 at49ld3200-13tc 86t commercial (0 to 70 c) 150 0.05 at49ld3200-13ti 86t industrial (-40 to 85 c) 50 150 0.05 AT49LD3200-20TC 86t commercial (0 to 70 c) 150 0.05 at49ld3200-20ti 86t industrial (-40 to 85 c) package type 86t 86-lead, thin small outline package (tsop type ii)
38 at49ld3200(b) 1940b ? 11/01 packaging information 86t ? tsop type ii 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 86t, 86-lead (10.16 mm body width) thin small outline package (tsop type ll) b 86t 10/18/01 0? ~ 8? pin 1 identifier pin 1 c gage plane l1 seating plane l a a1 a2 e1 e d b e notes: 1. this package conforms to jedec reference mo-142, variation ec. 2. dimensions d and e1 do not include mold protrusion. allowable protrusion on e1 is 0.25 mm per side and on d is 0.15 mm per side. 3. lead coplanarity is 0.10 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 22.12 22.22 22.32 note 2 e 11.56 11.76 11.96 e1 10.06 10.16 10.26 note 2 l 0.40 0.50 0.60 l1 0.25 basic b 0.17 0.22 0.27 c 0.12 0.21 e 0.50 basic
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